Co-Design Strategy With Low-C Consideration for On-Chip ESD Protection in RF ICs
نویسندگان
چکیده
Co-design strategy with low-capacitance (low-C) consideration for on-chip ESD protection in RF ICs is a solution to mitigate RF performance degradations caused by ESD protection device. A low-C design on ESD protection device was presented in this paper. An RF power amplifier (PA) codesigned with the low-C ESD protection device was also presented in this paper. Before ESD stress, RF performances of ESD-protected PA were as well as those of the unprotected PA. After ESD stress, the unprotected PA is seriously degraded, whereas the ESD-protected PA still kept the performances well. Co-design strategy with low-C consideration for on-chip ESD protection in RF ICs will continually be the important design task to accomplish RF ESD protection in CMOS technology.
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